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preliminary lvcmos/lvttl clock divider ICS87001-01 idt? / ics? lvcmos/lvttl fanout buffer 1 ics87001bg-01 rev. a may 1, 2009 general description the ICS87001-01 is a low skew, 1, 2 3, 4 5, 6 8, 16 lvcmos/lvttl fanout buffer/divider and a member of thehiperclocks? family of high performance clock solutions from idt. the ICS87001-01 has selectable clock inputs that accept single ended input levels. output enable pin controls whether the output is in the active or high impedance state. the ICS87001-01 is characterized at 3.3v, 2.5v and mixed 3.3v/2.5v, 3.3v/1.8v, 2.5v/1.8 v input/output supply operating modes.guaranteed part-to-part skew characteristics make the ICS87001-01 ideal for those applications demanding well defined performance and repeatability. features ? one lvcmos / lvttl output, 15 ? output impedance ? selectable lvcmos / lvttl clock inputs ? maximum output frequency: 250mhz ? part-to-part skew: tbd ? power supply modes: core/output 3.3v/3.3v 3.3v/2.5v 3.3v/1.8v 2.5v/2.5v 2.5v/1.8v ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s n output divider n2:n0 0 0 0 1 (default) 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 8 1 1 1 16 0 1 3 q oe n2:n0 clk1 clk0 clk_sel pulldown pulldown pulldown pulldown pullup 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 n0 n1 n2 clk1 clk_sel clk0 v dd oe v ddo nc q nc gnd nc nc gnd pin assignment block diagram the preliminary information presented herein represents a product in pre-production. the noted characteristics are based on ini tial product characterization and/or qualification. integrated device technology, incorporated (idt) reserves the ri ght to change any circuitry or specifications without notice. ICS87001-01 16-lead tssop 4.4mm x 3.0mm x 0.925mm package body g package to p v i e w
idt? / ics? lvcmos/lvttl fanout buffer 2 ics87001bg-01 rev. a may 1, 2009 ICS87001-01 lvcmos/lvttl clock divider preliminary table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function tables table 3. programmable output divider function table number name type description 1 oe input pullup output enable. when low, output s are in high impedance state. when high, outputs are active. lv cmos / lvttl interface levels. 2v dd power power supply pin. 3, 5 clk0, clk1 input pulldown single-ended clo ck input. lvcmos/lvttl interface levels. 4 clk_sel input pulldown clock select input. when high, selects clk1 input. when low, selects clk0 input. lvcmos / lvttl interface levels. 6, 7, 8 n2, n1, n0 input pulldown n divider pins . lvcmos/lvttl interface levels. see table 3. 9, 12 gnd power power supply ground. 10, 11, 13, 15 nc unused no connect. 14 q output single-ended clock output. 15 ? output impedance. lvcmos/lvttl interface levels. 16 v ddo power output supply pin. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? c pd power dissipation capacitance 10 pf r out output impedance 15 ? inputs n divider value output frequency (mhz) n2 n1 n0 0 0 0 1 (default) 250 001 2 125 010 3 83.333 011 4 62.5 100 5 50 101 6 41.667 110 8 31.25 1 1 1 16 15.625
ICS87001-01 lvcmos/lvttl clock divider preliminary idt? / ics? lvcmos/lvttl fanout buffer 3 ics87001bg-01 rev. a may 1, 2009 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v 5%,t a = 0c to 70c table 4b. power supply dc characteristics, v dd = 3.3v 5%, v ddo =2.5v 5%, t a = 0c to 70c table 4c. power supply dc characteristics, v dd = 3.3v 5%, v ddo =1.8v 0.15v, t a = 0c to 70c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 100.3 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 40 ma i ddo output supply current 1 ma symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 40 ma i ddo output supply current 1 ma symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 1.65 1.8 1.95 v i dd power supply current 40 ma i ddo output supply current 1 ma
idt? / ics? lvcmos/lvttl fanout buffer 4 ics87001bg-01 rev. a may 1, 2009 ICS87001-01 lvcmos/lvttl clock divider preliminary table 4d. power supply dc characteristics, v dd = v ddo = 2.5v 5%, t a = 0c to 70c table 4e. power supply dc characteristics, v dd = 2.5v 5%, v ddo =1.8v 0.15v, t a = 0c to 70c table 4f. lvcmos/lvttl dc characteristics, t a = 0c to 70c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information, output load test circuit diagrams. symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 39 ma i ddo output supply current 1 ma symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 1.65 1.8 1.95 v i dd power supply current 39 ma i ddo output supply current 1 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage v dd = 3.465v 2 v dd + 0.3 v v dd = 2.625v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v v dd = 2.625v -0.3 0.7 v i ih input high current clk0, clk1, n[2:0], clk_sel v dd = v in = 3.465v or 2.625v 150 a oe v dd = v in = 3.465v or 2.625v 5 a i il input low current clk0, clk1, n[2:0], clk_sel v dd = 3.465v or 2.625v, v in = 0v -5 a oe v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 v ddo = 3.3v 5% 2.6 v v ddo = 2.5v 5% 1.8 v v ddo = 1.8v 0.15v 1.5 v v ol output low voltage; note 1 v ddo = 3.3v 5% 0.5 v v ddo = 2.5v 5% 0.5 v v ddo = 1.8v 0.15v 0.4 v i ozl output hi-z current low -5 a i ozh output hi-z current high 5a
ICS87001-01 lvcmos/lvttl clock divider preliminary idt? / ics? lvcmos/lvttl fanout buffer 5 ics87001bg-01 rev. a may 1, 2009 ac electrical characteristics table 5a. ac characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices operating a the same supply volt age and with equal load conditions . using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: this parameters are guaranteed by ch aracterization. not tested in production. table 5b. ac characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices operating a the same supply volt age and with equal load conditions . using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: this parameters are guaranteed by ch aracterization. not tested in production. symbol parameter test conditions minimum typical maximum units f max output frequency 250 mhz t pd propagation delay, low to high; note 1 4.3 ns t sk(pp) part-to-part skew; note 2, 3 ps t r / t f output rise/fall time; note 4 20% to 80% 700 ps odc output duty cycle 50 % t en output enable time; note 4 5ns t dis output disable time; note 4 5ns symbol parameter test conditio ns minimum typical maximum units f max output frequency 250 mhz t pd propagation delay, low to high; note 1 4.6 ns t sk(pp) part-to-part skew; note 2, 3 ps t r / t f output rise/fall time; note 4 20% to 80% 800 ps odc output duty cycle 50 % t en output enable time; note 4 5ns t dis output disable time; note 4 5ns
idt? / ics? lvcmos/lvttl fanout buffer 6 ics87001bg-01 rev. a may 1, 2009 ICS87001-01 lvcmos/lvttl clock divider preliminary table 5c. ac characteristics, v dd = 3.3v 5%, v ddo = 1.8v 0.15v, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices oper ating a the same supply voltage and with equal load conditions . using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: this parameters are guaranteed by ch aracterization. not tested in production.. table 5d. ac characteristics, v dd = v ddo = 2.5v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices oper ating a the same supply voltage and with equal load conditions . using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: this parameters are guaranteed by ch aracterization. not tested in production. symbol parameter test conditions minimum typical maximum units f max output frequency 250 mhz t pd propagation delay, low to high; note 1 5ns t sk(pp) part-to-part skew; note 2, 3 ps t r / t f output rise/fall time; note 4 20% to 80% 1 ns odc output duty cycle 50 % t en output enable time; note 4 5ns t dis output disable time; note 4 5ns symbol parameter test conditions minimum typical maximum units f max output frequency 250 mhz t pd propagation delay, low to high; note 1 4.7 ns t sk(pp) part-to-part skew; note 2, 3 ps t r / t f output rise/fall time; note 4 20% to 80% 900 ps odc output duty cycle 50 % t en output enable time; note 4 5ns t dis output disable time; note 4 5ns
ICS87001-01 lvcmos/lvttl clock divider preliminary idt? / ics? lvcmos/lvttl fanout buffer 7 ics87001bg-01 rev. a may 1, 2009 table 5e. ac characteristics, v dd = 2.5v 5%, v ddo = 1.8v 0.15v, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? 250mhz unless noted otherwise. note 1: measured from the v dd /2 of the input to v ddo /2 of the output. note 2: defined as skew between outputs on different devices oper ating a the same supply voltage and with equal load conditions . using the same type of input on each device, the output is measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: this parameters are guaranteed by ch aracterization. not tested in production. symbol parameter test conditio ns minimum typical maximum units f max output frequency 250 mhz t pd propagation delay, low to high; note 1 5ns t sk(pp) part-to-part skew; note 2, 3 ps t r / t f output rise/fall time; note 4 20% to 80% 1.1 ns odc output duty cycle 50 % t en output enable time; note 4 5ns t dis output disable time; note 4 5ns
idt? / ics? lvcmos/lvttl fanout buffer 8 ics87001bg-01 rev. a may 1, 2009 ICS87001-01 lvcmos/lvttl clock divider preliminary parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit 3.3v core/1.8v lvcmos output load ac test circuit 2.5v core/1.8v lvcmos output load ac test circuit 3.3v core/2.5v lvcmos output load ac test circuit 2.5v core/2.5v lvcmos output load ac test circuit part-to-part skew scope qx lvcmos gnd v dd, 1.65v5% -1.65v5% v ddo scope qx lvcmos gnd v ddo v dd 0.9v0.075v -0.9v0.075v 2.4v5% scope qx lvcmos gnd v ddo v dd 0.9v0.075v -0.9v0.075v 1.6v5% scope qx lvcmos gnd v dd v ddo 2.05v5% -1.25v5% 1.25v5% scope qx lvcmos gnd v dd, 1.25v5% -1.25v5% v ddo t sk(pp) v ddo 2 v ddo 2 part 1 part 2 qx qy
ICS87001-01 lvcmos/lvttl clock divider preliminary idt? / ics? lvcmos/lvttl fanout buffer 9 ics87001bg-01 rev. a may 1, 2009 parameter measurement in formation, continued propagation delay output duty cycle/pulse width/period output rise/fall time application information recommendations for unused input pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clk inputs for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. t pd v dd 2 v ddo 2 q clk0, clk1 t period t pw t period odc = v ddo 2 x 100% t pw q 20% 80% 80% 20% t r t f q
idt? / ics? lvcmos/lvttl fanout buffer 10 ics87001bg-01 rev. a may 1, 2009 ICS87001-01 lvcmos/lvttl clock divider preliminary reliability information table 6. ja vs. air flow table for a 16 lead tssop transistor count the transistor count for ICS87001-01: 2781 package outline and package dimensions package outline - g suffix for 16 lead tssop table 7. package dimensions for 16 lead tssop reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ICS87001-01 lvcmos/lvttl clock divider preliminary idt? / ics? lvcmos/lvttl fanout buffer 11 ics87001bg-01 rev. a may 1, 2009 ordering information table 8. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 87001bg-01 87001b01 16 lead tssop tube 0 c to 70 c 87001bg-01t 87001b01 16 lead tssop 2500 tape & reel 0 c to 70 c 87001bg-01lf 7001b01l ?lead-free? 16 lead tssop tube 0 c to 70 c 87001bg-01lft 7001b01l ?lead-free? 16 lead tssop 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. th is product is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliabilit y or other extraordinary environmental requirements are not recommended without additional processing by idt. idt rese rves the right to change any circuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments.
ICS87001-01 lvcmos/lvttl clock divider preliminary www.idt.com ? 2009 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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